View ICS8741004AG_2918059.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

differential-to-lvds/0.7v differential pci express? jitter attenuator ics8741004 idt? / ics? pci express? jitter attenuator 1 ICS8741004AG rev. a august 3, 2007 general description the ics8741004 is a high performance differential-to-lvds/0.7v differential jitter attenuator designed for use in pci express? systems. in some pci ex press systems, such as those found in desktop pcs, the pci express clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the pll synthesizer and from the system board. the ics8741004 has 3 pll bandwidth modes: 200khz, 600khz and 2mhz. the 200khz mode will provide maximum jitter attenuation, but with higher pll tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. the 600khz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. the 2mhz bandwidth provides the best tracking skew and will pass most spread prof iles, but the jitter attenuation will not be as good as the lower bandwidth modes. because some 2.5gb serdes have x20 multipliers while others have x25 multipliers, the ics8741004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100mhz input/125mhz output) using the f_sel pins. the ics8741004 uses idt?s 3 rd generation femtoclock? pll technology to achieve the lowest possible phase noise. the device is packaged in a 24 lead tssop package, making it ideal for use in space constrained applications such as pci express add-in cards. pll bandwidth features ? two lvds and two 0.7v differential output pairs bank a has two lvds output pairs and bank b has two 0.7v differential output pairs ? one differential clock input pair ? clk, clk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency range: 98mhz - 160mhz ? input frequency range: 98mhz - 128mhz ? vco range: 490mhz - 640mhz ? cycle-to-cycle jitter: 35ps (maximum) ? full 3.3v operating supply ? three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages pin assignment ics8741004 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package top view bw_sel 0 = pll bandwidth: ~200khz float = pll bandwidth: ~600khz (default) 1 = pll bandwidth: ~2mhz hiperclocks? ic s 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 qa1 qa1 v ddo qa0 qa0 mr bw_sel nc v dda f_sela v dd oea qb1 qb1 v ddo qb0 qb0 iref f_selb oeb gnd gnd clk clk
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 2 ICS8741004AG rev. a august 3, 2007 block diagram f_sela 0 5 (default) 1 4 f_selb 0 5 (default) 1 4 vco 490 - 640 mhz phase detector m = 5 (fixed) qa0 qa0 qa1 qa1 pullup pullup pulldown float pulldown oea oeb f_sela f_selb bw_sel clk clk mr iref pullup pulldown pulldown qb0 qb0 qb1 qb1 0 = ~200khz float = ~400khz 1 = ~800khz
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 3 ICS8741004AG rev. a august 3, 2007 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 24 qa1 , qa1 output differential output pair. lvds interface levels. 3, 22 v ddo power output supply pins. 4, 5 qa0, qa0 output differential output pair. lvds interface levels. 6 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs q[ax:bx] to go low and the inverted outputs q[ax:bx] to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos/lvttl interface levels. 7 bw_sel input pullup/ pulldown pll bandwidth input. lvcmos/lvttl interface levels. see table 3b. 8 nc unused no connect. 9v dda power analog supply pin. 10 f_sela input pulldown frequency select pins for qax/qax outputs. lvcmos/lvttl interface levels. see table 3c. 11 v dd power core supply pin. 12 oea input pullup output enable for qax pins. when high, qax/qax outputs are enabled. when low, the qax/qax outputs are in a high impedance state. lvcmos/lvttl interface levels. see table 3a. 13 clk input pulldown non-inverting differential clock input. 14 clk input pullup inverting differential clock input. 15, 16 gnd power power supply ground. 17 oeb input pullup output enable for qbx pins. when high, qbx/qbx outputs are enabled. when low, the qbx/qbx outputs are in a high impedance state. lvcmos/lvttl interface levels. see table 3a. 18 f_selb input pulldown frequency select pins for qbx/qbx outputs. lvcmos/lvttl interface levels. see table 3c. 19 iref input a fixed precision resistor (rref = 475 ? ? ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 4 ICS8741004AG rev. a august 3, 2007 function tables table 3a. output enable function table table 3b. pll bandwidth function table absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c inputs outputs oea oeb qa[0:1]/qa[0:1] qb[0:1]/qb[0:1] 0 0 hi-z hi-z 1 1 enabled enabled input pll bandwidth bw_sel 0 ~200khz float ~600khz (default) 1~2mhz item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance,
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 5 ICS8741004AG rev. a august 3, 2007 table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c table 4c. differential dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c note 1: common mode input voltage is defined as v ih . table 4d. lvds dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage oea, oeb, mr, f_sela, f_selb 2v dd + 0.3 v bw_sel v dd ? 0.3 v dd + 0.3 v v il input low voltage oea, oeb, mr, f_sela, f_selb -0.3 0.8 v bw_sel -0.3 +0.3 v v im input mid voltage bw_sel v dd /2 ? 0.1 v dd /2 + 0.1 v i ih input high current f_sela, f_selb, mr, bw_sel v dd = v in = 3.465v 150 a oea, oeb v dd = v in = 3.465v 5 a i il input low current mr, f_sela, f_selb, v dd = 3.465v, v in = 0v -5 a oea, oeb, bw_sel v dd = 3.465v, v in = 0v -150 a symbol parameter test conditions minimum typical maximum units i ih input high current clk v dd = v in = 3.465v 150 a clk v dd = v in = 3.465v 5 a i il input low current clk v dd = 3.465v, v in = 0v -5 a clk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input volt age; note 1 gnd + 0.5 v dd ? 0.85 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 290 390 490 mv ? ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 6 ICS8741004AG rev. a august 3, 2007 ac electrical characteristics table 5. 0.7v differential ac characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c note 1: this parameter is defined in accordance with jedec standard 65. note 2: defined as skew within a bank of outputs at the same voltage and with equal load conditions. parameter symbol test conditio ns minimum typical maximum units f max output frequency 98 160 mhz t jit(cc) cycle-to-cycle jitter; note 1 35 ps t sk(b) bank skew, note 2 30 ps v high output voltage high qbx/qbx 530 870 ps v low output voltage low qbx/qbx -150 ps v ovs max. voltage, overshoot qbx/qbx v high + 0.35 v v uds min. voltage, undershoot qbx/qbx -0.3 v v rb ringback voltage qbx/qbx 0.2 v v cross absolute crossing voltage qbx/qbx @ 0.7v swing 250 550 mv ? ? ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 7 ICS8741004AG rev. a august 3, 2007 parameter measureme nt information 3.3v hcsl output load ac test circuit differential input level cycle-to-cycle jitter 3.3v lvds output load ac test circuit bank skew output duty cycle/pulse width/period r ref = 475 ? ? ? ? ? ? ? ? ? ? ? t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles qa[0:1] , qb[0:1] qa[0:1], qb[0:1] scope qx nqx 3.3v5% power supply +? float gnd lvds v dda v dd, v ddo t sk(b) qx0 qx0 qx1 qx1 where x is either bank a or bank b t pw t period t pw t period odc = x 100% qa[0:1] , qb[0:1] qa[0:1], qb[0:1]
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 8 ICS8741004AG rev. a august 3, 2007 parameter measurement in formation, continued hcsl output rise/fall time differential output voltage setup lvds output rise/fall time offset voltage setup clock outputs 0.175v 0.525v 0.525v 0.175v t r t f v swing ? ? ? ? ? ? ? ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 9 ICS8741004AG rev. a august 3, 2007 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics8741004 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 ? figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ende d signal driving differential input v dd v dda 3.3v 10 ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 10 ICS8741004AG rev. a august 3, 2007 differential clock input interface the clk /clk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the hiperclocks clk/clk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use thei r termination recommendation. figure 3a. hiperclocks clk/clk input driven by an idt hiperclocks lvhstl driver figure 3c. hiperclocks clk/clk input driven by a 3.3v lvpecl driver figure 3b. hiperclocks clk/clk input driven by a 3.3v lvpecl driver figure 3d. hiperclocks clk/clk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 ? ? ? ? ? ? ? ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 11 ICS8741004AG rev. a august 3, 2007 recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? ? figure 4. in a 100 ? ? ? ? ? ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 12 ICS8741004AG rev. a august 3, 2007 recommended termination figure 5a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 ? figure 5b is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same pcb. all traces should all be 50 ?
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 13 ICS8741004AG rev. a august 3, 2007 power considerations this section provides information on power dissipa tion and junction temperature for the ics8741004. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics741004 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (45ma + 12ma) = 197.5mw power (lvds_output) max = v ddo_max * i ddo_max = 3.465v * 80ma = 227.2mw power (hcsl_output) max = 45.65mw * 2 = 91.3mw total power_ max = (3.465v, with all outputs switchin g) = 197.5mw + 277.2mw + 91.3mw = 556mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj =
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 14 ICS8741004AG rev. a august 3, 2007 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 6. figure 6. lvhstl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? ? ? ic vout rl 50 vddo
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 15 ICS8741004AG rev. a august 3, 2007 reliability information table 7. ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ics8741004 is: 1318 package outline and package dimension package outline - g suffix for 24 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 82.3c/w 78.0c/w 75.9c/w all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics8741004 differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 16 ICS8741004AG rev. a august 3, 2007 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8741004ag ICS8741004AG 24 lead tssop tray 0
www.idt.com ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future netw orks. contact: www.idt.com ics871004 differential-to-lvds/0.7 v differential pci expr ess? jitter attenuator

▲Up To Search▲

Price & Availability of ICS8741004AG

	To Download ICS8741004AG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .